1. Field of the Invention
The present invention relates to a processing apparatus, and in particular, to a processing apparatus which has processors for performing a plurality of different kinds of processing.
2. Description of the Related Art
Personal computers, workstations, and high-performance game consoles have been advancing in functionality and performance in recent years. Arithmetic processing apparatuses to be used therein have therefore been increasing in circuit scale. These arithmetic processing apparatuses typically comprise a CPU (Central Processing Unit) or other processors which perform general-purpose arithmetic processing, a processor which manages signal input and output, a processor which performs audio signal processing, and a graphics processor which performs image processing, as well as memories to be used and managed by the processors.
Under the circumstances, it has been a significant challenge to achieve cost reduction while integrating the processors and the memories needed to satisfy performance requirements. An embedded dynamic random access memory (eDRAM) is sometimes used in order to merge and integrate one processor and a memory to be managed by the processor into a single semiconductor substrate. The use of eDRAMs makes it possible to enjoy advantages such that there is no need for input and output buffers or wiring on printed circuit boards since the processors and the memories are formed on the same semiconductor substrate, and that broad bandwidth design becomes feasible.
Nevertheless, in recent arithmetic processing apparatuses, the processors that require high speed and high functionality, such as CPUs and graphics processors, have often been designed and manufactured using the most advanced processes of such as 0.13 μm, 0.11 μm, 90 nm, and the like in order to suppress a rise in chip area and power consumption ascribable to increased circuit scales. When the most advanced processes are used, the incorporation of DRAMs, which do not require integration to a level as high as the processors, can result in increased cost. In such situations, the eDRAM-based design is not necessarily optimal.
There has recently been a technology developed in which terminals called micro bumps, having diameters of several tens of micrometers, are arranged for the purpose of signal input and output and for power supply. The introduction of such a structure enables of the application of CoC (Chip on Chip) and SIS (System In Silicon) configurations. In a CoC configuration, a semiconductor chip is stacked on another semiconductor chip, and they are connected through micro bumps. In an SIS configuration, a plurality of silicon chips are arranged on a substrate called a silicon interposer and the silicon chips are connected to each other through the micro bumps and the silicon interposer. The CoC and SIS configurations using micro bumps make high-speed data transfer between chips possible.
Under the circumstances, for arithmetic processing apparatuses that incorporate a high-performance graphics processor and the like for handling three-dimensional graphics, it is a significant challenge to optimize the balance between performance and cost with respect to how to integrate a CPU which performs general-purpose arithmetic processing and application-specific processors which are dedicated and designed for specific processing such as graphics and input and output signal processing.